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Allwinner /D1H /TWI[2] /TWI_CCR

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Interpret as TWI_CCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0clk_n0clk_m0 (P50)clk_duty

clk_duty=P50

Description

TWI Clock Control Register

Fields

clk_n
clk_m
clk_duty

Setting duty cycle of clock as master

0 (P50): 50%

1 (P40): 40%

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data