Allwinner /D1H /TWI[2] /TWI_CCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TWI_CCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0clk_n0clk_m0 (P50)clk_duty

clk_duty=P50

Description

TWI Clock Control Register

Fields

clk_n
clk_m
clk_duty

Setting duty cycle of clock as master

0 (P50): 50%

1 (P40): 40%

Links

()